multi-state spin-torque transfer magnetic random access memory

ABSTRACT

A multi-state spin-torque transfer magnetic random access memory (STTMRAM) is formed on a film and includes a first magnetic tunneling junctions (MTJ) having a first fixed layer, a first sub-magnetic tunnel junction (sub-MTJ) layer and a first free layer. The first fixed layer and first free layer each have a first magnetic anisotropy. The STTMRAM further includes a non-magnetic spacing layer formed on top of the first MTJ layer and a second MTJ formed on top of the non-magnetic spacing layer. The second MTJ has a second fixed layer, a second sub-MTJ layer and a second free layer. The second fixed and second free layers each have a second magnetic anisotropy, wherein at least one of the first or second magnetic anisotropy is perpendicular to the plane of the film.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of U.S. patent applicationSer. No. 11/678,515 filed on Feb. 23, 2007, by Rajiv Yadav Ranjan andentitled “A High Capacity Low Cost Multi-State Magnetic memory” and U.S.patent application Ser. No. 11/866,830, filed on Oct. 3, 2007, by RajivYadav Rajiv and entitled “An Improved High Capacity Low Cost Multi-StateMagnetic Memory” and U.S. application Ser. No. 11/860,467, filed on Sep.24, 2007, by Rajiv Yadav Ranjan and entitled “Low Cost Multi-StateMagnetic Memory” and a continuation-in-part of U.S. patent applicationSer. No. 11/674,124 entitled “Non-Uniform Switching Based Non-VolatileMagnetic Base Memory”, filed on Feb. 12, 2007, the disclosure of whichis incorporated herein by reference, as though set forth in full.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to non-volatile magnetic memoryand particularly to multi-state magnetic memory having stacked magnetictunnel junction (MTJ) with at least one MTJ having a storage layer witha magnetization direction being substantially perpendicular to the planeof the wafer (or substrate).

2. Description of the Prior Art

It has become clear that non-volatile memories, such as non-volatilerandom access memories (NVRAMs) are finding increasingly newapplications, and that their notoriety would not only continue but thatit would explode due to the increasing demands in mobile devices andother applications. It is also believed that current volatile DRAM willbe replaced by the current-switching version or spin-torque transfermagnetic random access memory (STTMRAM), in the coming future.

It is really important that in order for STTMRAM to gain broadacceptance, the cost of the memory and hence the cell size to be smallerand scalable to smaller feature size such as below 65 nm.

One of the ways to achieve higher density is by storing more than onebit of digital information in a memory cell of magnetic memory designs.Such memory cells are commonly referred to as multi-state (ormulti-level) cells (MLCs). Current MLC designs include magnetic memorywith a storage layer with a magnetization direction that is in-plane orparallel to the plane of the substrate or wafer. Such MLCs suffer fromlow density and therefore higher costs.

Stated differently, current STTMRAM designs have storage layers with amagnetization direction that is parallel to the plane of the substrate.One of the key challenges for such type of designs using in-planemagnetization is that they cannot be scaled to lower feature sizes suchas below 65 nm. This is primarily because as the feature size reduces,the reduced memory bit size (for example: for 90 nm, the memory bit sizeis 90 nm×180 nm, but for 45 nm this would be 45 nm×90 nm) becomesthermally unstable due to the reduction in the volume. The PerpendicularSTTMRAM enables lower switching current (therefore lower programcurrent), higher thermal stability and higher density.

Moreover, perpendicular STTMRAM does not require in-plane elongatedmemory bit like in the case of in-plane STTMRAM, mentioned above.In-plane circular shape or square shape is typically preferred forperpendicular STTMRAM over an elongated shape because in the latter,features pose large manufacturing challenges especially at lowerlithography geometry, such as below 90 nm. On the other hand, circularshape memory bit shapes allow for lower lithography and higher capacitymemory, making the perpendicular STTMRAM a preferred choice for futureapplications. It should be pointed out that the perpendicular STTMRAMcan utilize high anisotropy magnetic alloys as compared to the STTMRAMhaving in-plane magnetization, leading to higher thermal stability andthereby enabling scalability down to below 30 nm.

What is needed is a multi-state current-switching version or spin-torquemagnetic random access memory (STTMRAM) having stacked magnetic tunneljunctions (MTJs).

SUMMARY OF THE INVENTION

To overcome the limitations in the prior art described above, and toovercome other limitations that will become apparent upon reading andunderstanding the present specification, the present invention disclosesa method and a corresponding structure for a multi-state magneticstorage memory device that is based oncurrent-induced-magnetization-switching having reduced switching currentwith high thermal stability in the magnetic memory.

Briefly, an embodiment of the present invention includes a multi-statespin-torque transfer magnetic random access memory (STTMRAM) is formedon a film and includes a first magnetic tunneling junctions (MTJ) havinga first fixed layer, a first sub-magnetic tunnel junction (sub-MTJ)layer and a first free layer. The first fixed layer and first free layereach have a first magnetic anisotropy. The STTMRAM further includes anon-magnetic spacing layer formed on top of the first MTJ layer and asecond MTJ formed on top of the non-magnetic spacing layer. The secondMTJ has a second fixed layer, a second sub-MTJ layer and a second freelayer. The second fixed and second free layers each have a secondmagnetic anisotropy, wherein at least one of the first or secondmagnetic anisotropy is perpendicular to the plane of the film.

These and other objects and advantages of the present invention will nodoubt become apparent to those skilled in the art after having read thefollowing detailed description of the preferred embodiments illustratedin the several figures of the drawing.

IN THE DRAWINGS

FIG. 1 shows relevant layers of a multi-state current-switching magneticmemory element 100 are shown, in accordance with an embodiment of thepresent invention.

FIG. 2 shows various states of the memory element 100.

FIG. 3 shows a graph of the level of resistance (R) of each of thelayers 118, 114, 110 and 106 (shown in the y-axis) vs. the state of thememory element 100.

FIG. 4 shows a graph 250 of the tunneling magneto resistance (TMR),shown in the y-axis, vs. the resistance area (RA). FIG. 5 shows.

FIG. 5 shows relevant layers of a multi-state current-switching magneticmemory element 600 are shown, in accordance with another embodiment ofthe present invention.

FIG. 6 shows relevant layers of a multi-state current-switching magneticmemory element 700, in accordance with yet another embodiment of thepresent invention.

FIG. 7 shows relevant layers of a multi-state current-switching magneticmemory element 800, in accordance with still another embodiment of thepresent invention.

FIG. 8 shows a program/erase circuit for programming and/or erasing thememory elements of the various embodiments of the present invention.

FIG. 9 shows a read circuit for reading the memory elements of thevarious embodiments of the present invention.

FIG. 10 shows relevant layers of multi-state STTMRAM 1100, in accordancewith an embodiment of the present invention.

FIG. 11 shows relevant layers of multi-state STTMRAM 1153, in accordancewith an embodiment of the present invention.

FIG. 12 shows relevant layers of multi-state STTMRAM 1155, in accordancewith an embodiment of the present invention.

FIG. 13 shows relevant layers of multi-state STTMRAM 1160, in accordancewith an embodiment of the present invention.

FIG. 14 shows relevant layers of multi-state STTMRAM 1164, in accordancewith an embodiment of the present invention.

FIG. 15 shows relevant layers of multi-state STTMRAM 1166, in accordancewith an embodiment of the present invention.

FIG. 16 shows relevant layers of multi-state STTMRAM 1170, in accordancewith an embodiment of the present invention.

FIG. 17 shows relevant layers of multi-state STTMRAM 1180, in accordancewith an embodiment of the present invention.

FIG. 18 shows relevant layers of multi-state STTMRAM 1192, in accordancewith an embodiment of the present invention.

FIG. 19 shows relevant layers of multi-state STTMRAM 1200, in accordancewith an embodiment of the present invention.

FIG. 20 shows relevant layers of multi-state STTMRAM 1300, in accordancewith an embodiment of the present invention.

FIG. 21 shows relevant layers of multi-state STTMRAM 1400, in accordancewith an embodiment of the present invention.

FIG. 22 shows relevant layers of multi-state STTMRAM 1500, in accordancewith an embodiment of the present invention.

FIG. 23 shows relevant layers of multi-state STTMRAM 1600, in accordancewith an embodiment of the present invention.

FIG. 24 shows relevant layers of multi-state STTMRAM 1700, in accordancewith an embodiment of the present invention.

FIG. 25 shows relevant layers of multi-state STTMRAM 1800, in accordancewith an embodiment of the present invention.

FIG. 26 shows a flow chart of the steps performed, during a write orprogram operation, to write/program the multi-state STTMRAM, inaccordance with an embodiment of the present invention.

FIG. 27( a) shows top-down or in-plane view and side-view of shapes thatany of the STTMRAMs 1100, 1153, 1155, 1160, 1164, 1166 or 1700 can havewhen their free and fixed layers have perpendicular magneticorientation.

FIG. 27( b) shows top-down or in-plane view and side-view of shapes thatany of the STTMRAMs 1100, 1153, 1155, 1160, 1164, 1166 or 1700 can havewhen their free and fixed layers have in-plane magnetic orientation.

Table 1 shows certain exemplary characteristics of the embodiments ofFIGS. 1, 5 and 6.

Table 2 shows certain exemplary characteristics of the embodiment ofFIG. 7.

DETAILED DESCRIPTION OF EMBODIMENTS

In the following description of the embodiments, reference is made tothe accompanying drawings that form a part hereof, and in which is shownby way of illustration of the specific embodiments in which theinvention may be practiced. It is to be understood that otherembodiments may be utilized because structural changes may be madewithout departing from the scope of the present invention.

In an embodiment of the present invention, a multi-state magnetic memorycell is disclosed. In one embodiment of the present invention, a stackof magnetic tunnel junction (MTJ) is formed, each MTJ being formed of atleast three layers, a barrier layer formed between a fixed layer and afree layer, each MTJ being separated from another by a conductive layer,the stack forming a multi-state magnetic memory cell for storing atleast two bits of digital information.

Referring now to FIG. 1, relevant layers of a multi-statecurrent-switching (or spin-torque) magnetic memory element 100 areshown, in accordance with an embodiment of the present invention. Thememory element 100 is shown to include a bottom electrode 122 on top ofwhich is shown formed a pinning layer 120 on top of which is shownformed a fixed layer 118, on top of which is shown formed a barrierlayer 116, on top of which is formed a free layer 114, on top of whichis shown formed a non-magnetic layer 112, on top of which is shownformed a free layer 110, on top of which is shown formed a barrier layer108, on top of which is shown formed a fixed layer 106, on top of whichis shown formed a pinning layer 104, on top of which is shown formed atop electrode 102. The top electrode 102 and the bottom electrode 122are each made of Tantalum (Ta) in an exemplary embodiment although othersuitable materials are contemplated. The layers 114, 116 and 118 areshown to form a MTJ 126 separated by the layer 112 from an MTJ 124,which is formed from the layers 106, 108 and 110. The MTJ 124 and 126form the relevant parts of a stack of memory elements. In fact, whiletwo MTJs are shown to form the stack of FIG. 1, other number of MTJs maybe stacked for storing additional bits of information.

In FIG. 1, the MTJ 126 is for storing a bit of information or twostates, ‘1’ and ‘0’, while the MTJ 124 is for storing another bit ofinformation and since each bit represents two binary states, i.e. ‘1’and ‘0’, two bits represent four binary states, generally represented as‘00’, ‘01’, ‘10’, ‘11’, or 0, 1, 2 and 3 in decimal notation,respectively. The memory element 100 advantageously stores two bits ofinformation thereby decreasing the real estate dedicated for memory andfurther increases system performance. This is particularly attractivefor embedded memory applications. Additionally, manufacturing is madeeasier and less costly and scalability is realized.

In FIG. 1, the barrier layers of each of the MTJs, such as the layer 116acts as a filter for electrons with different spins giving rise todifferent amounts of tunneling current for electrons with differentspins thereby causing two unique resistance values associated with eachMTJ for two different orientations of the free layer. In the case whereadditional MTJs are employed, each MTJ similarly has associatedtherewith, a unique resistance value.

In one embodiment of the present invention, the thickness of the layers108 and 116 to cause the MTJs 124 and 126 to have different resistancesand therefore capable of storing more than one bit.

Examples of materials used to form each of the layers of the memoryelement 100 will now be presented. It should be noted that thesematerials are merely examples and other types of materials may beemployed. The layers 104 and 120, are each typically formedsubstantially of IrMn or PtMn or NiMn or any other material includingManganese (Mn). The layers 106 and [120] 118 are typically formedsubstantially of a magnetic material. Examples of such magnetic materialinclude CoFeB or CoFe/Ru/CoFeB. The layers 108 and 116 are each madesubstantially of a non-magnetic material, an example of which ismagnesium oxide (MgO). The layer 112 is a non-magnetic layer madesubstantially of, for example, NiNb, NiP, NiV or CuZr. The layer 112serves to insulate the two MTJs 124 and 126 from one another. In anembodiment employing more than two MTJs, another layer, such as thelayer 112 would be formed on top of the layer 104 or on the bottom ofthe layer 120. The layers 110 and 114 are each made of CoFeB containingoxides intermixed. The layers 110 and 114 are substantially amorphous inan at-deposited state. The top electrode 102 and the bottom electrode122 are each made of tantalum (Ta), in one embodiment of the presentinvention, however, other types of conductive material may be employed.

The layers 120 and 104 are anti-ferromagnetic (AF) coupling layers. Morespecifically, for example, the magnetic moment of the layer 104 helps topin the magnetic moment of the layer 106. Similarly, the magnetic momentof the layer 120 serves to pin the magnetic moment of the layer 118. Themagnetic moment of each of the layers 120 and 104 are permanently fixed.

Other choices of material for the layers 108 and 116 are aluminum oxide(Al2O3) and titanium oxide (TiO2). A thin-layer of one of theconstituent elements may be deposited prior to the deposition of thebarrier oxide layer. For example, a 2-5 A thick Mg layer may bedeposited prior to the deposition of the layers 108 and 116. This limitsany damage of the magnetic-free layer from intermixing of the elementsduring deposition. The layer 112 is a non-magnetic layer which issubstantially amorphous made of, for example, Nickel niobium (NiNb),Nickel phosphorous (NiP), Nickel vanadium (NiV), Nickel borom (NiB) orcopper-zirconium (CuZr). It should be noted that the composition ofthese alloys is chosen in such a way that the resulting alloy becomessubstantially amorphous, for example, for nickel niobium (NiNb), thetypical Nb content is maintained between 30 to 70 atomic percent and fornickel phosphorous (NiP) the phosphorous (P) content is maintainedbetween 12 and 30 atomic percent. The layer 112 serves to isolate thetwo MTJs 124 and 126 from one another. In an embodiment of the presentinvention, which employs more than two MTJs, another layer, such as thelayer 112 would be formed on top of the layer 104 or on the bottom ofthe layer 120. The layers 110 and 114 are each made of CoFeB containingoxides intermixed. The layers 110 and 114 are substantially amorphous inan as-deposited state. The top and the bottom electrodes are typicallymade of tantalum (Ta).

The layers 120 and 104 are anti-ferromagnetic (AF) coupling layers. Morespecifically, for example, the magnetic moment of the layer 104 helps topin the magnetic moment of the layer 106. Similarly, the magnetic momentof the layer 120 serves to pin the magnetic moment of the layer 118. Themagnetic moment of each of the layers 120 and 104 are permanently fixed.This is typically done by a magnetic annealing process following thedeposition of all the layers and involves heating the wafer consistingof at least one memory element 100 under the application of asubstantially uni-axial magnetic field of over 5 kilo-Oersteds and atemperature of over 350 degree centigrade for typically 2 hours. Thisannealing process also serves to re-crystallize the layers 108 and 116and their respective adjacent free layers 110 and 114. This process isessential for making high performing magnetic tunnel junctions.

Typical thicknesses for each of the layers of the memory element 100 arenow presented. However, these sizes are merely examples, as otherthicknesses are anticipated. A typical thickness of each of the topelectrode 102 and the bottom electrode 122 is 30 to 200 nm. While apreferred thickness is typically 50 nm, the actual thickness choice maydepend on the requirements from the metallization process. The layers104 and 120 are typically 20 to 100 nm in thickness with a preferredthickness of 25-50 nm. The layers 108 and 118 are typically made ofthree layers of Cobalt-Iron (CoFe)/Ruthenium (Ru)/Cobalt-Iron-Boron(CoFeB) with CoFe layer being placed adjacent to the layers 104 and 120.The typical thickness of the CoFe layer is 3 to 10 nm, Ru layer is 0.6to 1.0 nm to create anti-ferromagnetic coupling between the two adjacentmagnetic layers of CoFe and CoFeB. The CoFeB layer is typically 2 to 10nm thick with a preferred range of 2.5 to 5 nm. The free layers 110 and114 are typically 2 to 7 nm thick with a preferred range of 2-5 nm andmay contain a 1-2 nm thick layer of Co—Fe-oxide inter-dispersed in thatlayer in order to get low switching current during current inducedswitching. The barrier layers 108 and 116 are typically 0.8 to 3 nm. Itis very likely that the two barrier layers may have slightly differentthickness, for example layer 116 can be 1.5 to 2.5 nm thick while thesecond barrier layer 108 may be 0.8 to 1.2 nm thick, and vice-versa.Additionally, the thickness and the amounts of oxide in the free-layers110 and 114 may be different by a factor of 1.5 or higher. Thenon-magnetic layer 112 is typically 2 to 50 nm thick with a preferredrange being 2 to 10 nm. It should be pointed out that while the [most]preferred material choice of the non-magnetic isolation layer 112consists of amorphous non-magnetic alloys, a crystalline non-magneticalloy may also work.

During manufacturing, the layers of the memory element 100 are formed inthe manner described hereinabove. Additionally, an annealing process,which is well known, is performed heating the memory element 100 in thepresence of a magnetic field after which channels are formed in each ofthe layers 108 and 116. Following the annealing process, the fixedlayers 106 and 118 are oriented in a particular orientations and thelayers 108 and 116, as well as the layers 110 and 114, take oncrystalline characteristics.

During operation, current is applied, in a perpendicular directionrelative to the plane of the paper of FIG. 1, either from a directionindicated by the arrow 128 or a direction indicated by the arrow 130.When current is applied, depending on the level of current, the magneticmoment of the layers 110 and 114 are each caused to be switched to anopposite direction, or not. Since the MTJs 124 and 126 are made withdifferent aspect ratios (or anisotropy), the switching current isdifferent for these two MTJs. For example, in one embodiment of thepresent invention, the aspect ratio for MTJ 124 is approximately 1:1.3to 1:1.5 while the aspect ratio for the MTJ 126 is approximately 1:2 to1:2.5. Therefore, the switching current for the MTJ 126 is 3-5 timeshigher than that of the MTJ 124, in the foregoing embodiment. At highcurrent levels both MTJs switch magnetic orientation, while at lowcurrent levels only the MTJ 124 having the smaller aspect ratioswitches.

The state of the magnetic moment of each of the layers of the MTJdefines the state of the memory element 100. As the layers 104 and 120each act as AF coupling layers, they pin or switch the magnetic momentsof the their neighboring fixed layer, which, then, by the application ofcurrent, causes neighboring free layers to switch or not. Morespecifically, the layer 118 defines one state, the layer 114 definesanother state, the layer 110 defines yet another state and the layer 106defines still another state. For the sake of understanding, the statesof each of the layers 118, 114, 110 and 106 are referred to as states 1,2, 3 and 4, respectively.

FIG. 2 shows various states of the memory element 100. Due to the use oftwo MTJs, four different states or two bits may be stored, therefore,the states 1-4 are shown. At each state, the directions of the arrowsindicate the direction of the magnetic moments of free layers andpinning layers. The direction of the arrow 200 shows the direction ofhigh current applied to the memory element 100 and in this case, thestate of the memory element 100 is at an all ‘1’s or all ‘0’s state. Thedirection of the arrow 202 shows the direction of low current applied tothe memory element 100 when at state 1. The direction of the arrow 204shows the direction of high current applied to the memory element 100when the latter is at state 2 and the direction of the arrow 206 showsthe direction of low current applied to the memory element 100 when atstate 3.

FIG. 3 shows a graph of the level of resistance (R) of each of thelayers 118, 114, 110 and 106 (shown in the y-axis) vs. the state of thememory element 100. Thus, at, for example, at 208, the memory element100 has taken on the state 1 (corresponding to 202 on FIG. 2), at 210,the memory element 100 has taken on the state 2 (corresponding to 204 onFIG. 2), at 212, the memory element 100 has taken on the state 3(corresponding to 206 on FIG. 2), and at 214, the memory element 100 hastaken on the state 4 (corresponding to 200 on FIG. 2). The level ofresistance for each of these states is indicated in Table 1, at a columnlabeled “Total R”. For example, at state 1, the R, in FIG. 3 isindicated as being 3 kilo ohms (K Ohms) by Table 1. At state 2, the R,in FIG. 3, is indicated as being 4 K Ohms and so on. The values used forresistance serve as examples only such that other values may be employedwithout departing from the scope and spirit of the present invention.

It should be noted that different aspect ratio or anisotropy associatedwith the different MTJs 124 and 126 causes the different switching ofthe MTJs, which results in two bits being stored in the memory element100. In other embodiments, some of which will be shortly presented anddiscussed, the size of the barrier layers of the MTJs are changed toeffectuate different resistances. In yet other embodiments, the size ofthe MTJs are changed to the same.

FIG. 4 shows a graph 250 of the tunneling magneto resistance (TMR),shown in the y-axis, vs. the resistance area (RA). The TMR is definedas:

TMR=(Rh−Rl)/Rl  Eq. (1)

Wherein Rh is resistance at a high state and Rl is resistance at a lowstate.

The graph 250 of FIG. 4 serves merely as an example to convey thedifference in TMR or percentage increase as the RA increases. Forinstance, at an RA of 2 ohm-micro-meters squared, the TMR is 100% whileat a RA of 10, the TMR is 150% where the thickness of the barrier layerof the MTJ is between 14-24 Angstroms.

FIG. 5 shows relevant layers of a multi-state current-switching magneticmemory element 600 are shown, in accordance with another embodiment ofthe present invention. The memory element 600 is shown to include abottom electrode 122 on top of which is shown formed a pinning layer 120on top of which is shown formed a fixed layer 118, on top of which isshown formed a barrier layer 116, on top of which is formed a free layer114, on top of which is shown formed a non-magnetic layer 112, as thatshown in FIG. 1. As previously indicated, relative to FIG. 1, the MTJ126 comprises the layers 114, 116 and 118. However, in the embodiment ofFIG. 5, the MTJ 612, which is made of a free layer 602, a barrier layer604 and a fixed layer 606, is smaller, in its planar dimension, than theMTJ 126 of FIG. 1, which causes the MTJ 612 to have a differentresistance than that of the MTJ 126.

In FIG. 5, the free layer 602 is shown to be formed on top of the layer112 and on top of the layer 602 is shown formed the layer 604, on top ofwhich is shown formed the layer 606, on top of which is shown formed apining layer 608, a top electrode 610. The MTJs 126 and 612 are shownseparated by the layer 112. The MTJs 126 and 612 form the relevant partsof a stack of memory elements. In fact, while two MTJs are shown to formthe stack of FIG. 5, other number of MTJs may be stacked for storingadditional bits of information.

The difference in the planar dimension of the MTJs 612 to that of theMTJ 126 is approximately 1 to 10 and typically 1 to 3, in one embodimentof the present invention. The material for each of the layers of thememory element 600 may be the same as that of counterpart layers of thememory element 100. For example, the layer 602 is made of the samematerial as that of the layer 110 and the layer 604 is made of the samematerial as that of the layer 108 and the layer 606 is made of the samematerial as the layer 106 and the layer 608 is made of the same materialas the layer 104. The top electrodes 610 and 102 are made of the samematerial. In another embodiment, the MTJ 612 may be larger, in size, inthe same planar dimension, than the MTJ 126.

The operation of the embodiment of the embodiment of FIG. 5 is the sameas that of FIG. 1.

FIG. 6 shows relevant layers of a multi-state current-switching magneticmemory element 700, in accordance with yet another embodiment of thepresent invention. The memory element 700 to include a bottom electrode122 on top of which is shown formed a pinning layer 120 on top of whichis shown formed a fixed layer 118, on top of which is shown formed abarrier layer 116, on top of which is formed a free layer 114, on top ofwhich is shown formed a non-magnetic layer 112, as that shown in FIGS. 1and 6. As previously indicated, relative to FIGS. 1 and 6, the MTJ 126comprises the layers 114, 116 and 118. However, in the embodiment ofFIG. 6, the MTJ 714, which is shown to comprise a free layer 710, abarrier layer 708 and a fixed layer 706, is shown to be smaller in itsplanar dimension than the MTJ 126 causing the MTJ 714 to have adifferent resistance than that of the MTJ 126.

The MTJs 126 and 714 are shown separated by the layers 702 and 704.Although the layer 704 serves to pin the layer 706 while the layer 702serves to isolate the MTJ 126 and is an amorphous only to the layer 114.The layer 702, in one embodiment of the present invention, is made oftwo non-magnetic layers, such as Ta and/or an amorphous alloy, the sameas Nickel-niobium (NiNb) or nickel-phosphorus (NiP). The MTJs 126 and612 form the relevant parts of a stack of memory elements. In fact,while two MTJs are shown to form the stack of FIG. 5, other number ofMTJs may be stacked for storing additional bits of information.

The difference in the planar dimension of the MTJs 714 to that of theMTJ 126 is 1 to 10, and typically 1 to 3 in one embodiment of thepresent invention. The material for each of the layers of the memoryelement 700 may be the same as the counterpart layers of the memoryelement 100 or that of the memory element 600. For example, the layer710 is made of the same material as that of the layer 110 and the layer708 is made of the same material as that of the layer 108 and the layer706 is made of the same material as the layer 106 and the layer 704 ismade of the same material as the layer 104. The top electrodes 712 and102 are made of the same material. In another embodiment, the MTJ 714may be larger in size in the same planar dimension, than the MTJ 126.

FIG. 7 shows relevant layers of a multi-state current-switching magneticmemory element 800, in accordance with still another embodiment of thepresent invention. In FIG. 7, the memory element 800 is shown to includea bottom electrode 802 on top of which is shown formed a pinning layer804 on top of which is shown formed two fixed layers on either sidethereof. That is, a fixed layer 806 is shown formed on one side of thelayer 804 and a fixed layer 808 is shown formed on an opposite side ofthe layer 804.

In FIG. 7, two MTJs are shown formed on either side or top of the layer804. Namely, an MTJ 820 is shown formed on one side of the layer 804 andanother MTJ 822 is shown formed on an opposite side of the layer 804.The MTJ 820 includes the fixed layer 806, which is formed on top of thelayer 804 and the barrier layer 810 shown formed on top of the layer 806and the free layer 812 shown formed on top of the layer 810. The MTJ 822is shown to include the fixed layer 808, which is formed on top of thelayer 804 and the barrier layer 814, which is shown formed on top of thelayer 808 and the free layer 816, which is shown formed on top of thelayer 814. A top electrode 818 is shown formed on top of the MTJs 820and 822, or more specifically on top of the layers 812 and 816. The topelectrode 818 is typically made of two layers, such as Ta and aconductive, non-magnetic material.

In forming the memory element 800, the layer 804 is formed on top of thebottom electrode and the layers of the MTJs 820 and 822 are formed ontop of the layer 804 and on top of the MTJs 820 and 822 is formed thetop electrode 818. The layers of the MTJs 820 and 822 are formeduniformly and continuously on top of the layer 804 and a trench 824,which is basically an empty space or hole is formed, prior to depositingthe top electrode 818, by etching through the layers of the MTJs 820 and822. In this manner, the fixed layers of the MTJs 820 and 822 are thesame layer prior to etching and the barrier layers of the MTJs 820 and822 are the same layer prior to etching and the free layers of the MTJs820 and 822 are the same layer prior to etching.

In one embodiment of the present invention, the trench 824 is filledwith a dielectric material, such as silicon dioxide (SiO2) or siliconnitride (SiNx) to enhance stability.

After etching, the top electrode 818 is deposited or formed on top ofthe MTJs 820 and 822. The embodiment of FIG. 7, as the embodiments ofFIGS. 6, 5, and 1 store two bits of information, with [on]one bit storedin each MTJ. Thus, the MTJ 820 is for storing one bit and the MTJ 822 isfor storing another bit of information. However, more bits may be storedby adding MTJs. In FIG. 7, additional MTJs may be added on top of thelayer 804 or the MTJs 820 and 822. With the addition of MTJs, beyondthat which is shown in FIG. 7, additional trenches are formed betweenthe MTJs, such as the trench 824.

Table 2 shows certain exemplary characteristics of the embodiment ofFIG. 7. It should be noted that similarly, Table 1 shows certainexemplary characteristics of the embodiments of FIGS. 1, 5 and 6.

For example, in Table 2, under the “Total R” column, there is shown theresistance at each state of the memory element 800, such as the state 1,the state 2, the state 3 and the state 4. As previously noted, eachstate represents a binary value such that four states, and representedby two bits are stored. The programming current, in micro amps, i.e. thecurrent needed to program the memory element 800 to a given state, isindicated in the last column of Table 2, under the label “Prog I”.

In an alternative embodiment of the present invention, a non-uniformswitching based non-volatile magnetic memory element, such as thenon-uniform switching based non-volatile magnetic memory element 100disclosed in U.S. patent application Ser. No. 11/674,124 entitled“Non-Uniform Switching Based Non-Volatile Magnetic Base Memory”, filedon Feb. 12, 2007, may be employed to replace the MTJs of the variousembodiments shown and discussed herein. For example, the MTJ 124 or theMTJ 126 may be replaced with a non-uniform switching based non-volatilemagnetic memory element. Other MTJs discussed herein may also bereplaced with non-uniform switching based non-volatile magnetic memoryelement. This advantageously further reduces the requisite switchingcurrent to enhance system performance.

FIG. 8 shows a program/erase circuit for programming and/or erasing thememory elements of the various embodiments of the present invention. InFIG. 8, a current source 902 is shown coupled to a current mirrorcircuit 904, which is shown coupled to the switch 906, which is, inturn, shown coupled to the switch 968, which is shown coupled to themulti-state current-switching magnetic memory cell 914, which is showncoupled to the switch 916. Further shown in FIG. 8, a current source 918is shown coupled to a current mirror circuit 920 and further showncoupled to Vcc on an opposite end thereto. The circuit 920 is furthershown coupled to the switch 999.

The circuit 904 is shown to include a P-type transistor 922, a P-typetransistor 924 and a P-type transistor 926. The source of each of thetransistors 922, 924 and 926 are shown coupled to Vcc. Vcc is at apredetermined voltage level that is higher than ground. The gate of thetransistor 922 is shown coupled to the current source 902 and theopposite side of the current source 902 is shown coupled to ground. Thedrain of the transistor 922 is shown coupled to its gate as well as tothe gate of the transistor 924 and the gate of the transistor 926. Thedrains of the transistors 924 and 926 are shown coupled to the switch906. The memory cell 914 is shown to include an MTJ 910, an MTJ 912 andan access transistor 940. The MTJ 912 is shown coupled in series to theMTJ 912, which is shown coupled to the drain of the transistor 940. Thegate of the transistor 940 is shown coupled to the word line 942. Theword line 942 selects a memory cell. The source of the transistor 940 isshown coupled to the switch 916.

While memory cell 914 is shown to include two MTJs coupled in series, itis contemplated that the memory cell 914 can include more than two MTJsand that which would be coupled together in series. In this case, eachMTJ may have a different switching current associated therewith.

The circuit 920 is shown to include an N-type transistor 928, an N-typetransistor 930 and an N-type transistor 932. The drains of thetransistors 928, 930 and 932 are shown coupled to ground. The gate ofthe transistor 932 is coupled to the current source 918 and is furthercoupled to the drain of the transistor 932 and is further coupled to thegate of the transistor 930 as well as to the gate of the transistor 928.The drain of the transistors 930 and 928 are shown coupled to the switch999.

Each of the switches 968 and 916 are shown operative to switch betweentwo states, a program state and an erase state. The switches 906 and 999are shown operative to switch between two states.

The MTJs 910 and 912 are similar to the MTJs of previous figures, suchas those depicted in FIGS. 1 and 6. In an alternative embodiment, theMTJs 910 and 912, coupled in parallel, would be similar to the MTJsshown in FIG. 7. Each MTJ 910 and 912 possesses a resistance of adifferent or unique value. The difference in their resistance resultsfrom the difference in the aspect ratio or size or anisotropy of theMTJs.

The size of the transistor 926 is greater than the size of thetransistors 922 and 924. Similarly, the size of the transistor 928 isgreater than the size of the transistors 930 and 932. In one embodimentof the present invention, the size difference of the foregoingtransistors is 4 to 1. To explain the operation of programming, anexample is provided with fixed values but it should be noted that thesevalues may be altered without departing from the scope and spirit of thepresent invention.

In operation, to program the memory cell 914 to a state 1, a current oflevel of 50 micro Amps is applied by the current source 902 to thecircuit 904, which is amplified to 4× the current level or 200microAmps, as shown in Table 1 because the transistor 926 is able todrive this level of current. This causes the switch 906 to switch to thestate indicated at 944. The switch 908 is set to ‘program’ state, as isthe switch 916, which causes the 200 micro amp current to flow throughthe MTJs 910 and 912 and the transistor 940 is selected by raising thevoltage on the word line 942. This results in programming of state 1.The magnetic moment of the free layers of the MTJs 910 and 912 will becaused to be aligned with the magnetic moment of that of theirrespective fixed layers. This results in the lowest resistance of thememory cell 914, as indicated in Table 1.

In programming the memory cell 914 to a state 2, a current of level of50 micro Amps is applied by the current source 918 to the circuit 920,which is the same current level as that generated by the circuit 920.The current level for state 2 is indicated in Table 1. The switch 999 iscaused to be switched to the state indicated at 948. The switches 908and 916 are both set to ‘erase’ state, which causes the 50 micro ampcurrent to flow through the MTJs 910 and 912 and the transistor 940 isselected by raising the voltage on the word line 942. This results inprogramming of state 2. The magnetic moment of the free layer of the MTJ910 is caused to be switched to an anti-parallel state or a state thatis in opposite to being aligned with its respective fixed layer. The MTJ912 remains in the state it was in at state 1. The reason for this is,that in one embodiment of the present invention, with the aspect ratioof the MTJ 912 being higher than that of MTJ 910, it is prevented fromswitching. This results in the resistance of the memory cell 914indicated in Table 1.

In programming the memory cell 914 to a state 3, a current of level of50 micro Amps is applied by the current source 918 to the circuit 920,which causes the current level, generated by the transistor 928 to be 4times that of the level of the current source, or 200 micro amps. Thecurrent level for state 3 is indicated in Table 1. The switch 910 iscaused to be switched to the state indicated at 950. The switches 908and 916 are both set to ‘erase’ state, which causes the 200 micro ampcurrent to flow through the MTJs 910 and 912 and the transistor 940 isselected by raising the voltage on the word line 942. This results inprogramming of state 3. The magnetic moment of the free layers of theMTJs 910 and 912 are caused to be switched to an anti-parallel staterelative to their respective fixed layers. This results in theresistance of the memory cell 914 to be that indicated in Table 1.

To program the memory cell 914 to a state 4, a current of level of 50micro Amps is applied by the current source 902 to the circuit 904,which is the current level of the circuit 904 and that which isindicated in Table 1 for state 4. This causes the switch 906 to switchto the state indicated at 946. The switch 908 is set to ‘program’ state,as is the switch 916, which causes the 50 micro amp current to flowthrough the MTJs 910 and 912 and the transistor 940 is selected byraising the voltage on the word line 942. This results in programming ofstate 4. The magnetic moment of the free layer of the MTJ 910 will becaused to be aligned with the magnetic moment of that of its respectivefixed layer. The MTJ 912 remains in its anti-parallel state, the reasonfor this is due the difference in the aspect ratios of the two MTJs asdiscussed hereinabove. This results in a resistance of the memory cell914 indicated in Table 1.

FIG. 9 shows a read circuit for reading the memory elements of thevarious embodiments of the present invention. FIG. 9 is shown to includea memory cell 1002 coupled to a sense amplifier circuit 1004, which isshown coupled to a reference circuit 1006. The memory cell 1002 is shownto include an access transistor 1008, an MTJ 1010 and an MTJ 1012. Thetransistor 1008 is shown to have a drain, a source and a gate. The gateof the transistor 1008 is shown coupled to a word line 1014, the drainof the transistor is shown coupled to ground and the source of thetransistor is shown coupled to the MTJ 1010.

It should be noted that wherever values are indicated herein, they areto merely serve as examples with the understanding that other suitablevalues are anticipated. It is further noted that while reference is madeto an N-type or P-type transistor, either type or other suitable typesof transistors may be employed, as the type of transistor indicated inthe foregoing embodiments, merely serve as examples.

The circuit 1006 is shown to include a number of state referencecircuits, indicated as state reference circuit 1020, 1022 and 1024. Eachof the circuits 1020-1024 includes an access transistor and a referenceresistor. For example, the circuit 1020 is shown to include a referenceresistor 1026 coupled on one side to the circuit 1004 and Vcc and on theother side to the drain of an access transistor 1028. The gate of thetransistor 1028 is shown coupled to a select signal, namely select 1signal 1040.

Similarly, the circuit 1022 is shown to include a reference resistor1030 coupled on one side to the circuit 1004 and Vcc and on the otherside to the drain of an access transistor 1032. The gate of thetransistor 1032 is shown coupled to a select signal, namely the select 2signal 1042. The circuit 1024 is shown to include a reference resistor1034 coupled on one side to the circuit 1004 and Vcc and on the otherside to the drain of an access transistor 1036. The gate of thetransistor 1044 is shown coupled to a select signal, namely the select 3signal 1044.

The MTJs 1010 and 1012, as stated relative to FIG. 8, are similar to theMTJs of the embodiments of the present invention except that in the caseof FIG. 7, the MTJs of the read circuit would be coupled in parallelrather than in series, shown in FIG. 9.

During a read operation, the memory cell 1002 is selected by raising thevoltage of the word line 1014. The circuit 1004 compares the totalresistance of the MTJs 1010 and 1012 with the resistances of thereference resistors of the state reference circuits. For example, theresistance of the MTJs 1010 and 1012 (collectively or added together) iscompared to the resistance of the resistor 1026 and if it is determinedto be less, the state of the memory cell 1002 is declared as binaryvalue ‘00’ or perhaps, state 1. However, if the resistance of the MTJs1010 and 1012, collectively, is determined to be higher than that of theresistor 1026, the former is then compared to the resistance of theresistor 1030 and there again, if the resistance of the MTJs 1010 and1012 is less than the resistor 1030, the state 2 or binary value ‘01’.If the resistance of the MTJs 1010 and 1012 is determined to be greaterthan the resistor 1030, the resistance of the MTJs 1010 and 1012 iscompared to the resistance of the resistor 1034 and if the resistance ofthe former is determined to be lower, the state 3 or binary value ‘10’is declared (or read), otherwise, the state 4 or binary value ‘11’ isdeclared.

The select signal of each of the circuits 1020-1024 are used to selectthe corresponding circuit. For example, to compare the resistance of theMTJs to the resistance of the resistor 1026, the signal 1040 isactivated thereby turning on the transistor 1028. In the meanwhile, theremaining transistors of the circuit 1006 are off. Similarly, to comparethe resistance of the MTJs to the resistance of the resistor 1030, thesignal 1042 is activated thereby turning on the transistor 1032. In themeanwhile, the remaining transistors of the circuit 1006 are off. Tocompare the resistance of the MTJs to the resistance of the resistor1034, the signal 1044 is activated thereby turning on the transistor1036. In the meanwhile, the remaining transistors of the circuit 1006are off.

Examples of resistance values of the reference resistors are averages ofthe resistances of the MTJs 1010 and 1012. For example, the resistanceof the resistor 1026 is the average of the resistances of the MTJs 1010and 1012 at the states 1 and 4, as indicated in Table 1. The resistanceof the resistor 1030 is the average of the resistances of the MTJs 1010and 1012 at the states 2 and 4, as indicated in Table 1. The resistanceof the resistor 1034 is the average of the resistances of the MTJs 1010and 1012 at the states 2 and 3, as indicated in Table 1. For example, inone embodiment of the present invention, the resistor 1026 has aresistance of 3.5 kilo-ohm, which is the average of 3 and 4 kilo-ohms.The resistance of the resistor 1030 is 4.5 kilo-ohms, which is theaverage of 5 and 4 kilo-ohms and the resistance of the resistor 1034 is5.5 kilo-ohms, which is the average of 5 and 6 kilo-ohms.

In various embodiments of the present invention, some of which aredisclosed hereinbelow, a STTMRAM using two or more MTJs havingperpendicular orientations or a combination of perpendicular andlongitudinal MTJs, placed in the close proximity to each other isdisclosed. One of the characteristics of such a STTMRAM is toadvantageously have multiple resistances associated therewith allowingfor the storage of multiple states, thereby having smaller cell size.

At smaller litho dimensions the magnetic memory bits would havesubstantially perpendicular orientation of the magnetization direction.

Bottom MTJ (or stack) is a memory structure where the fixed layer isformed below the free layer during MTJ fabrication and a top MTJ (orstack) is memory structure where the fixed layer is formed on top of thefree layer during MTJ fabrication.

FIG. 10 shows a multi-state spin-torque transfer magnetic random accessmemory (STTMRAM) 1100, in accordance with an embodiment of the presentinvention. The multi-state STTMRAM memory 1100 is shown to includebottom electrode (BE) 1104, underlayer 1106, fixed layer 1108, spinpolarization enhanced (interface) layers (SPEL) 1110 and 1114, freelayer 1118, cap layer 1120, non-magnetic spacing layer 1122, underlayer1128, fixed layer 1130, SPEL 1134, tunneling layer 1136, SPEL 1138, freelayer 1140, cap layer 1141 and top electrode (TE) 1143.

Underlayer 1106 is shown formed on top of BE 1104, which is generallyformed on a substrate or film (or a metal post or line such as tungsten,aluminum or copper for) of a typical integrated circuit. Fixed layer1108 is shown formed on top of fixed layer 1108 and SPEL layer 1110 isshown formed on top of fixed layer 1108.

In some embodiments, SPELL 110 is a part of fixed layer 1108. In someembodiments, SPELL 114 is a part of free layer 1118.

Referring still to FIG. 10, tunneling layer 1112 is shown formed on topof SPELL 110, SPEL 1114 is shown formed on top of tunneling layer 1112,free layer 1118 is shown formed on top of SPEL 1114, cap layer 1120 isshown formed on top of free layer 1118, non-magnetic spacing layer 1122is shown formed on top of cap layer 1120, underlayer 1128 is shownformed on top of non-magnetic spacing layer 1122, fixed layer 1130 isshown formed on top of underlayer 1128, SPEL 1134 is shown formed on topof fixed layer 1130, tunneling layer 1136 is shown formed on top of SPEL1134, SPEL 1138 is shown formed on top of tunneling layer 1136, freelayer 1140 is shown formed on top of SPEL 1138, cap layer 1141 is shownformed on top of free layer 1140 and TE 1143 is shown formed on top ofcap layer 1141.

Magnetic tunnel junction (MTJ) 1124 comprises fixed layer 1108, SPELL1110, tunneling layer 1112, SPEL 1114 and free layer 1118. MTJ 1126comprises fixed layer 1130, SPEL 1134, tunneling layer 1136, SPEL 1138and free layer 1140. In this manner, MTJ 1126 and MTJ 1124 are stacked.While MTJ 1124 and MTJ 1126 are each shown to have a bottom stackingstructure with their respective free layers formed above their fixedlayers, alternatively, they may have a top stacking structure wheretheir respective fixed layers are formed above their free layers.

While two MTJs are shown in FIG. 10, it is understood that any number ofMTJs may be stacked.

SEPL 1134, tunneling layer 1136 and SPEL 1138, are collectively referredto as sub-magnetic tunnel junction (sub-MTJ) layer 1132. Similarly, SEPL1110, tunneling layer 1112 and SPEL 1114 are collectively referred to assub-magnetic tunnel junction (sub-MTJ) layer 1159.

ULs 1106 and 1128, in some embodiments, may be multi-layered with one ormore layers of underlayer or at least one layer of seed layer. Seedlayers are well known to those skilled in the art.

In some embodiments, SPELs are not employed in either of MTJs 1124 or1126, in other embodiments, one of the MTJs 1124 or 1126 employs SPELsand another does not. In yet another embodiment, only one SPEL is usedadjacent to the tunneling layer. That is, for example, only SPEL 1110 isused and SPEL 1114 is absent or only SPEL 1114 is used and SPEL 1110 isabsent. In yet other embodiments, as discussed above, SPEL is part of anadjacent layer. For example, SPEL 1134 is part of fixed layer 1130 orSPEL 1138 is part of free layer 114 or SPEL 1134 is part of fixed layer1130 and SPEL 1138 is part of free layer 1140.

The functions of BE 1104 and TE 1143 are as known to those skilled inthe art. Fixed layers 1108 and 1130 each have a magnetization direction(or orientation) that is fixed at the time of manufacturing andthroughout the operational lifetime of the multi-state STTMRAM cell1100. The magnetization direction of each of the free layers 1118 and1140 switches between a parallel state and an anti-parallel staterelative to the magnetization direction of each of their respectivefixed layers during operation of the multi-state STTMRAM 1100. In fact,the parallel and anti-parallel states define the logical state of a freelayer which define the logical state of the corresponding MTJ. Forexample, free layer 1118's magnetization state being in a parallel staterelative to fixed layer 1108 defines a different logical state than freelayer 1118's magnetization direction being in an anti-parallel staterelative to fixed layer 1108. An example of logic states are ‘0’ or ‘1’.

The direction of magnetization of fixed layer 1108, which is shown bythe arrow 1123, is fixed in the direction of the arrow 1123 and it isperpendicular to the surface of the substrate onto which the multi-stateSTTMRAM 1100 is formed. The direction of magnetization of free layer1118, which switches relative to that of fixed layer 1108, as shown bythe arrow 1127, is also perpendicular to the plane of the substrate.

In some embodiments, the thickness of each of underlayers 1106 and 1128is typically between 5 nano meters (nm) to 50 nm and may comprise aseedlayer underneath or in between BE 1104 and underlayer 1106 and inbetween non-magnetic spacing layer 1122 and underlayer 1128. In someembodiments, the seedlayer thickness is 2 nm to 50 nm. In someembodiments, fixed layers 1108 and 1130 are 2 nm to 100 nm. In someembodiments, the thickness of SPEL layer is typically less than 5 nm. Insome embodiments, the thickness of each of the free layers 1118 and 140is typically 1 to 10 nm. In some embodiments, the thickness of each oftunneling layers 1112 and 1136 is typically 0.5 to 3.0 nm. In someembodiments, the thickness of non-magnetic isolation layer 1122 is 5nm-100 nm. In some embodiments, the thickness of caplayer 1141 is 2 to100 nm and typically 5 to 50 nm. In some embodiments, the thickness oftop electrode 1143 and bottom electrode choice and thickness depend onthe device design and are typically thicker than 10 nm.

The material of which each of the underlayers 1106 and 1128 is made ofare typically chosen form alloys of one or more of the elements chosenfrom tantalum (Ta), chromium (Cr), titanium (Ti), molybedenum (Mo),tungsten (W), boron (B), copper (Cu), nitrogen (N), nickel (Ni), carbon(C), phosphorus (P), iron (Fe), or cobalt (Co) and should be conductingand non-magnetic. Fixed layers 1108 and 1130 are each generally alloysof iron (Fe) nickel (Ni) cobalt (Co), platinum (Pt), copper (Cu), boron(B), tantalum (Ta), titanium (Ti), chromium (Cr) including rare earthalloys like terbium (Tb), samarium (Sm), niodynium (Nd), and galadinium(Gd). In one embodiment, the magnetic alloy also contains one or more ofsilicon oxide (SiO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), andaluminum oxide (Al2O3). In yet another embodiment, each of fixed layers1108 and 1130 is comprised of multi-layer of Co and Pt with each layertypically having a thickness of 0.3 nm-2 nm, and having less than 10multi-layers. The choice of material for each of SPEL layers 1110, 1114,1134 and 1138, in some embodiments, is an alloy of Co (20-80 at%)F(20-80 at % eB(8-25 at %) such that the as deposited SPEL layeris >80 volume percent amorphous. The choice of material for each oftunneling layers 1112 and 1136 is one or combinations from aluminumoxide (Al2O3), titanium oxide (TiO2), magnesium oxide (MgO), strontitumoxide (SrO), or ruthenium oxide (RuO). Cap layers 1120 and 1141 are eacha nonmagnetic alloy and conducting of one or more of the elementsselected from tantalum (Ta), chromium (Cr), tungsten (W), titanium (Ti),zirconium (Zr), niobium (Nb), copper (Cu), or aluminum (Al).

The function UL 1106 is to provide the proper crystal structure templatein order to grow the adjacent and subsequent magnetic fixed layers 1108and 1130 having perpendicular orientation in a direction shown by arrow1123. This is typically characterized by measuring the delta theta 50 ofthe preferred easy axis. As known to those skilled in the art, this iscarried out typically by using an x-ray diffractometer such as onedesigned by Rigaku Coporation, Tokyo, Japan. A smaller delta-theta 50indicates, such as typically below 5 degrees, a more oriented film. Atypical value of the delta-theta 50 is below 10 degrees. The function ofSPEL layer is to enhance the tunneling magneto-resistance (TMR) of theMTJs through proper crystal structure matching during the magneticannealing process.

The function of fixed layers 1108 and 1130 is to act as a referencelayer for respective magnetic tunnel junction (MTJ). For example, fixedlayer 1108 acts as a reference layer with fixed magnetic orientation forMTJ 1124 and fixed layer 1140 acts as a reference layer with fixedmagnetic orientation for MTJ 1126.

The function of each of tunneling layers 1112 and 1136 is to act asspin-filter layer for the spin tunneling for the MTJ which is importantto get high TMR. More specifically, the tunneling layers selectivelyfilter the spin states of the polarized conduction electrons as theytravel through the fixed layer to the free layer and vice versa. Adetailed description of this can be found in the published paper,“Theory of Tunneling Magnetoresistance For Epitaxial Systems by W. H.Butler, X. G. Zhang, S. Vutukuri, M. Chchiev and T. C. Schulthess, IEEETrans Mag., vol. 41, No. 10, October 2005”.

The function of each of free layers 1118 and 1140 is to switch betweenmagnetic orientations (states) when current is applied to themulti-state STTMRAM thereby storing a state. The free layer is criticalto its corresponding MTJ in that it causes the MTJ to exhibit hightunneling magneto resistance (TMR) characteristic. The design and thematerial of choice used for making the free layer determines, at leastin part, the programming current of the multi-state STTMRAM as well asdevice reliability, more specifically the thermal stability.

While STTMRAM 1100 is shown to include two MTJs, in other embodiments,it may include more than two MTJs. In fact, any number of MTJs may beemployed in any of the STTMRAM of the various embodiments of the presentinvention. In the case where more than two MTJ are employed, a uniqueswitching current switches the state of each MTJ. For example, a STTMRAMwith three MTJs, coupled in series, and coupled to an n-channel MOSFEL(NMOS) type of access transistor may exhibit switching currents of 75micro Amps for one MTJ, 50 micro Amps for a second MTJ and 25 micro Ampsfor the third MTJ.

It is noted that an MTJ is a variable resistive element. In this regard,any of the MTJs discussed and/or shown herein may be replaced with avariable resistive element without departing from the scope and spiritof the present invention.

In operation, during a write operation, electric current is applied in adirection that is either from BE 1104 through the subsequent layers thatare on top of BE 1104 or in a direction from TE 1143 through thesubsequent layers formed below TE 1143.

It is noted that the direction of magnetization of the free and fixedlayers of the MTJs in the FIGS. 10 through 25 is indicated by thedirection of the arrows used therein.

FIG. 11 shows a multi-state STTMRAM 1153, in accordance with analternative embodiment of the present invention. The multi-state STTMRAM1153 includes MTJ 1126, which is shown formed on top of theanti-ferromagnetic (AFM) layer 1128, which is shown formed top of UL1150 The top portion of the multi-state STTMRAM 1153, i.e., the layerson top of the fixed layer 1130 are analogous to common layers of that ofmulti-state STTMRAM 1100.

Anti-ferromagnetic (AFM) layer 1128 is shown formed on top of UL 1150,which is shown formed on top of non-magnetic spacing layer 1152 which isformed on top of the cap layer 1120, which is shown formed on top offree layer 1118, which is shown formed on top of SPEL 1114. The layersformed below SPEL 1114 are analogous to that of like locations ofmulti-state STTMRAM 1100. AFM layer 1148 is shown formed between UL 1106and fixed layer 1108. UL 1106 is shown formed on top of BE 1104, whichis typically formed on film or substrate of an integrated circuit. Inthis respect, the embodiment of FIG. 11 is analogous to that of FIG. 10except that each AFM layer separates its respective MTJ from thecorresponding UL.

Each of the AFM layer is used to establish perpendicular orientation ofits respective fixed layer. In some embodiments, each of the AFM layer1148 and 1128 is made of material chosen from one or more of thefollowing: Iridium manganese (IrMn), platinum manganese (PtMn), nickelmanganese (NiMn) and iron manganese (FeMn) and has atypical thicknessbetween 2 to 50 nm.

FIG. 12 shows a multi-state STTMRAM 1155, in accordance with analternative embodiment of the present invention. Layers 1128, 1122,1120, 1118, 1114, 1112, 1110, 1108, 1106 and 1104 are analogous to thoseof multi-state STTMRAM 1100. On top of UL 1128, there is shown formedfixed layer 1130 and on top of fixed layer 1130, there is shown formedSPEL 1134. On top SPEL 1134, three is shown formed tunneling layer 1136and on top of tunneling layer 1136, there is shown formed SPEL 1138. Ontop of SPEL 1138, there is shown formed free layer 1140 and on top offree layer 1140, there is shown formed AFM layer 1154. On top of AFMlayer 1154, there is shown formed cap layer 1141 and on top of cap layer1141, there is shown formed TE 1143.

AFM layer 1154 is analogous to AFM layers 1148 and 1128.

FIG. 13 shows a multi-state STTMRAM 1160, in accordance with analternative embodiment of the present invention. The multi-state STTMRAM1160 is shown to include MTJ 1124, formed on top of UL 1106, which isformed on top of BE 1104, as in the embodiment of FIG. 10. On top of MTJ1124 is shown formed cap layer 1120 on top of which is formednon-magnetic spacing layer 1122. On top of non-magnetic spacing layer1122 is shown formed UL 1128. On top of UL 1128 is shown formed fixedlayer 1130 and on top of fixed layer 1130 is shown formed sub-MTJ stack1132. On top of sub-MTJ stack 1132 is shown formed a composite freelayer 1157. Composite free layer 1157 comprises of layers 1158, layer1160 and layer 1156. Each of layers 1158 and 1156 is analogous to layer1118.

Layer 1160 is also known as a nano-current channel (NCC) layer and iscomprised of magnetic and non-magnetic regions as depicted by the darkerrectangles and white or no-color rectangles. The darker rectangularregions represent the magnetic regions and the while rectangular regionsrepresent the non-magnetic regions although vice versa is contemplated.The magnetic part is typically an alloy of one or more of the elementschosen from Co, Fe, Ni, Ti, Ta, Cr, Si, B, P, C, W, Al, Zr and thenon-magnetic portion is one or more of oxides, nitrides and phosphidesof Al, Si, Ti, Ta, W, Zr.

The layers 1158, 1160 and 1162, in combination, are referred to hereinas composite free layer 1157, as are similarly structured layers where aNCC is formed between two free layers.

In one embodiment, composite free layer 1157 comprises of layers 1158and 1160. In another embodiment, composite free layer 1157 comprises oflayers 1160 and 1156. In a yet another embodiment, composite free layer1157 comprises of layers 1158, 1160 and 1156, and the layer 1156 isthinner than layer 1158 by more than a factor of two.

It is expected that the MTJ2 1162 of multi-state STTMRAM 1160 has lowerprogramming current than the MTJ1 1124 by over a factor of two times.

FIG. 14 shows a multi-state STTMRAM 1164, in accordance with anotherembodiment of the present invention. The top portion of the multi-stateSTTMRAM 1164 is analogous to the top portion of multi-state STTMRAM1100. AFM layer 1128 is shown formed on top of UL 1150, which is shownformed on top of the non-magnetic spacing layer 1152 which is formed ontop of cap layer 1120, which is shown formed on top of composite freelayer 1157, which is shown formed on top of sub-MTJ layer 1159, which isshown formed on top of layer 1108, which is shown formed on top of AFMlayer 1148, which is shown formed on top of UL 1106, which is shownformed on top of BE 1104. The layers 1108, sub-MTJ layer 1159 and thecomposite free layer 1157 form MTJ 1161.

In operation, the MTJ1 1161 requires a lower programming current thanthe MTJ2 1126.

FIG. 15 shows a multi-state STTMRAM 1166, in accordance with anotherembodiment of the present invention. In FIG. 15, UL 1106 is shown formedon top of BE 1104. On top of UL 1106 is shown formed MTJ 1124 and on topof MTJ 1124 is shown formed cap layer 1120. On top of cap layer 1120 isshown formed non-magnetic spacing layer 1122 and on top of layer 1122 isshown formed UL 1128. On top of UL 1128 is shown formed composite freelayer 1157 and on top of the composite free layer 1157 is shown formedthe sub-MTJ layer 1132. On top of sub-MTJ layer 1132 is shown formedfixed layer 1163 and on top of fixed layer 1163 is shown formed AFMlayer 1154. On top of AFM layer 1154 is shown formed cap layer 1141 andon top of cap layer 1141 is shown formed TE 1143. The layers 1157, 1132,1163 and 1154 collectively comprise MTJ 1161.

In the embodiment of FIG. 15, MTJ 1161 is shown formed on top of MTJ1124 therefore creating a stacked MTJ structure. As with all embodimentsshown in FIGS. 10 through 25, while two MTJs are shown to be stacked, invarious embodiments of the present invention, any number of MTJs may bestacked.

As earlier stated, the magnetization of fixed layers 1108 and 1163 is ina direction shown by the arrows 1123 and 1126, respectively. In oneembodiment, non-magnetic spacer layer 1122 is made thicker than 20 nm toensure no magnetic interactions between the MTJ 1124 and MTJ 1161.

FIG. 16 shows a multi-state STTMRAM 1170, in accordance with analternative embodiment of the present invention. In the embodiment ofFIG. 16, MTJ 1126 is shown stacked on top of MTJ 1176. MTJ is shownformed on top of UL 1106, which is shown formed on top of BE 1104. Caplayer 1120 is shown formed on top of MTJ 1176 and on top of cap layer1120 is shown formed non-magnetic spacing layer 1122. On top ofnon-magnetic spacing layer 1122 is shown formed UL 1128 and on top of UL1128 is shown formed MTJ 1126. On top of MTJ 1126 is shown formed caplayer 1141 and on top of cap layer 1141 is shown formed TE 1143.

MTJ 1176 is shown formed of fixed layer 1172, SPEL 1171, tunneling layer1178, SPEL 1173, and free layer 1174. Fixed layer 1172 is formed on topof the AFM layer 1179, which is shown formed on top of the UL 1106.Unlike the MTJs of FIGS. 10 through 15 where the direction ofmagnetization of the free layers and fixed layers were perpendicular tothe surface of the substrate (perpendicular magnetic anisotropy), thedirection of magnetization of the free and fixed layers of MTJ 1176 areparallel or in-plane relative to the surface of the substrate on whichthe a multi-state STTMRAM 1170 is built. In the case where more than twoMTJs are stacked, there may be an MTJ with in-plane magnetic anisotropyformed on top of MTJ 1126 and an MTJ with perpendicular magneticanisotropy formed on top it and so on with alternating magneticanisotropy. Alternatively, there may be an MTJ with perpendicularanisotropy formed on top of MTJ 1126 and on top of it is formed anin-plane magnetic anisotropy MTJ where the MTJs of varying magneticanisotropy skip by two. Alternatively, the MTJs may skip by any number.

FIG. 17 shows a multi-state STTMRAM 1180, in accordance with yet anotherembodiment of the present invention. In the embodiment of FIG. 17, UL1106 is shown formed on top of BE 1104 and on top of UL 1106 is shownformed MTJ 1124. On top of MTJ 1124 is shown formed cap layer 1120 andon top of cap layer 1120 is shown formed MTJ 1190. On top of MTJ 1190 isshown formed cap layer 1141 and on top of cap layer 1141 is shown formedTE 1143.

MTJ 1190 is shown comprised of: AFM layer 1187, fixed layer 1183, SPEL1182, tunneling layer 1184, SPEL 1186 and free layer 1185. Fixed layer1183 is shown formed on top of AFM layer 1187, SPEL 1182 is shown formedon top of fixed layer 1183, tunneling layer 1184 is shown formed on topof SPEL 1182, SPEL 1186 is shown formed on top of tunneling layer 1184and free layer 1185 is shown formed on top of SPEL 1186. SPEL 1182,tunneling layer 1184 and SPEL 1186 collectively comprise sub-MTJ layer1188. As in the embodiment of FIG. 16, non-magnetic spacing layer 1122separates the two MTJs of FIG. 17.

FIG. 18 shows a multi-state STTMRAM 1192, in accordance with yet anotherembodiment of the present invention. The multi-state STTMRAM is shown toinclude BE 1104, UL 1106, AFM layer 1196, fixed layer 1172, sub-MTJlayer 1175, free layer 1174, cap layer 1120, non-magnetic spacing layer1122, AFM layer 1150, MTJ 1126, cap layer 1141 and TE 1143. In theembodiment of FIG. 18, UL 1106 is shown formed on top of BE 1104, MTJ1194 is shown formed on top of UL 1106, cap layer 1120 is shown formedon top of MTJ 1194, non-magnetic spacing layer 1122 is shown formed ontop of cap layer 1120, non-magnetic spacing layer 1122 is shown formedon top of AFM layer 1150, MTJ 1126 is shown formed on top of AFM layer1150, cap layer 1141 is shown formed on top of MTJ 1126 and TE 1143 isshown formed on top of cap layer 1141.

Layers 1196, 1172, 1175, free layer 1174 collectively comprise MTJ 1194.

The direction of magnetization of each of the fixed layer 1172 and freelayer 1174, of MTJ 1194, is parallel relative to the surface of thesubstrate onto which multi-state STTMRAM 1192 is made, whereas, the freeand fixed layers of MTJ 1126 each have a direction of magnetization thatis perpendicular to the plane of the substrate onto which multi-stateSTTMRAM 1192 is formed. Accordingly, the embodiment of FIG. 18 shows anMTJ with a perpendicular magnetic anisotropy formed on top of one havingan in-plane magnetic anisotropy.

FIG. 19 shows multi-state STTMRAM 1200, in accordance with analternative embodiment of the present invention. The multi-state STTMRAM1200 is shown to include BE 1104, UL 1106, MTJ 1124, cap layer 1120,non-magnetic spacing layer 1122, MTJ 1190, cap layer 1141 and TE 1143.MTJ 1190 is shown to include AFM layer 1250, fixed layer 1240, sub-MTJlayer 1232 and free layer 1230. The sub-MTJ layer 1232 is shown toinclude SPEL 1238, tunneling layer 1236 and SPEL 1234.

UL 1106 is shown formed on top of BE 1104. MTJ 1124 is shown formed ontop of UL 1106, cap layer 1120 is shown formed on top of MTJ 1124,non-magnetic spacing layer 1122 is shown formed on top of cap layer1120, and MTJ 1190 is shown formed on top of non-magnetic spacing layer1122. Cap layer 1141 is shown formed on top of MTJ 1190 and TE is shownformed on top of cap layer 1141.

More specifically, AFM layer 1250 is shown formed on top of non-magneticspacing layer 1122, fixed layer 1240 is shown formed on top of AFM layer1250, SPEL 1238 is shown formed on top of fixed layer 1240, tunnelinglayer is shown formed on top of SPEL 1238, SPEL 1234 is shown formed ontop tunneling layer 1236 and free layer 1230 is shown formed on top ofSPEL 1234.

The direction of magnetization of each of free layer 1230 and fixedlayer 1240 is in-plane relative to the plane of the substrate.Accordingly, the embodiment of FIG. 19 shows an MTJ with an in-planemagnetic anisotropy formed on top of one having a perpendicular magneticanisotropy.

FIG. 20 shows multi-state STTMRAM 1300, in accordance with anotherembodiment of the present invention. In the embodiment of FIG. 20,multi-state STTMRAM memory 1300 is shown to include BE 1104, UL 1106,MTJ 1194, cap layer 1120, non-magnetic spacing layer 1122, UL 1128, MTJ1162, cap layer 1141 and TE 1143. UL 1106 is shown formed on BE 1104,MTJ 1194 is shown formed on top of UL 1106, cap layer 1120 is shownformed on top of MTJ 1194, non-magnetic spacing layer 1122 is shownformed on top of cap layer 1120, UL 1128 is shown formed on top ofnon-magnetic spacing layer 1122, MTJ 1162 is shown formed on top of UL1128, cap layer 1141 is shown formed on top of MTJ 1162, cap layer 1141is shown formed on top of MTJ 1162 and TE is shown formed on top of caplayer 1141.

In FIG. 20, the magnetic anisotropy of each of the free and fixed layersof MTJ 1162 is perpendicular and the magnetic anisotropy of each of thefree and fixed layers of MTJ 1194 is in-plane.

FIG. 21 shows multi-state STTMRAM 1400, in accordance with anotherembodiment of the present invention. In the embodiment of FIG. 21,multi-state STTMRAM 1400 is shown to include BE 1104, UL 1106, MTJ 1161,cap layer 1120, non-magnetic spacing layer 1122, UL 1128, MTJ 1190, caplayer 1141 and TE 1143. UL 1106 is shown formed on BE 1104, MTJ 1161 isshown formed on top of UL 1106, cap layer 1120 is shown formed on top ofMTJ 1161, non-magnetic spacing layer 1122 is shown formed on top of caplayer 1120, UL 1128 is shown formed on top of non-magnetic spacing layer1122, MTJ 1190 is shown formed on top of UL 1128, cap layer 1141 isshown formed on top of MTJ 1190, cap layer 1141 is shown formed on topof MTJ 1190 and TE is shown formed on top of cap layer 1141.

In FIG. 21, the magnetic anisotropy of each of the free and fixed layersof MTJ 1190 is in-plane and the magnetic anisotropy of each of the freeand fixed layers of MTJ 1161 is perpendicular.

FIG. 22 shows multi-state STTMRAM 1500, in accordance with anotherembodiment of the present invention. In the embodiment of FIG. 22,multi-state STTMRAM 1500 is shown to include BE 1104, UL 1106, MTJ 1502,cap layer 1120, non-magnetic spacing layer 1122, UL 1150, AFM layer1128, MTJ 1126, cap layer 1141 and TE 1143. UL 1106 is shown formed onBE 1104, MTJ 1502 is shown formed on top of UL 1106, cap layer 1120 isshown formed on top of MTJ 1502, non-magnetic spacing layer 1122 isshown formed on top of cap layer 1120, UL 1150 is shown formed on topcap layer 1120, AFM layer 1128 is shown formed on top of UL 1150, MTJ1126 is shown formed on top of AFM layer 1128, cap layer 1141 is shownformed on top of MTJ 1126, and TE 1143 is shown formed on top of caplayer 1141.

MTJ 1502 is shown to include AFM layer 1196, fixed layer 1172, sub-MTJlayer 1175, free layer 1512 and composite free layer 1514. Compositefree layer 1514 is shown to include free layer 1169, NCC 1510 and freelayer 1514. The free layers positioned above and below the NCC layer aresometimes referred to as “sub-free layers”. For example, free layer 1169and free layer 1508 may be each referred to as sub-free layer 1169 andsub-free layer 1508, respectively.

AFM layer 1196 is shown formed on top of UL 1106, fixed layer 1172 isshown formed on top of AFM layer 1196, sub-MTJ layer 1175 is shownformed on top of fixed layer 1172, free layer 1512 is shown formed ontop sub-MTJ layer 1175, composite free layer 1514 is shown formed on topof free layer 1172, and cap layer 1120 is shown formed on top ofcomposite free layer 1514. Composite free layer 1514 is formed of NCC1510 formed on top of free layer 1169 and free layer 1508 is shownformed on top of NCC 1510. In one embodiment, the layer 1172 is

In FIG. 22, the magnetic anisotropy of each of the layers 1172 and 1512is in-plane while the magnetic anisotropy of each of the free and fixedlayers of MTJ 1126 is perpendicular.

FIG. 23 shows multi-state STTMRAM 1600, in accordance with anotherembodiment of the present invention. In the embodiment of FIG. 23,multi-state STTMRAM 1600 is shown to include BE 1104, UL 1106, MTJ 1124,cap layer 1120, non-magnetic spacing layer 1122, UL 1128, MTJ 1602, caplayer 1141 and TE 1143. UL 1106 is shown formed on BE 1104, MTJ 1124 isshown formed on top of UL 1106, cap layer 1120 is shown formed on top ofMTJ 1124, non-magnetic spacing layer 1122 is shown formed on top of caplayer 1120, MTJ 1602 is shown formed on top of non-magnetic spacinglayer 1122 cap layer 1141 is shown formed on top of MTJ 1602, and TE1143 is shown formed on top of cap layer 1141.

MTJ 1602 is analogous except that it is formed on top of MTJ 1124 andmore specifically, on top of non-magnetic spacing layer 1122. Thus, NCC1606 is analogous to NCC 1514.

In FIG. 23, the magnetic anisotropy of each of the free and fixed layersof MTJ 1602 is in-plane and the magnetic anisotropy of each of the freeand fixed layers of MTJ 1124 is perpendicular.

FIG. 24 shows multi-state STTMRAM 1700, in accordance with anotherembodiment of the present invention. In the embodiment of FIG. 24,multi-state STTMRAM 1700 is shown to include BE 1104, UL 1106, MTJ 1161,cap layer 1120, non-magnetic spacing layer 1122, UL 1128, MTJ 1162, caplayer 1141 and TE 1143. UL 1106 is shown formed on BE 1104, MTJ 1161 isshown formed on top of UL 1106, cap layer 1120 is shown formed on top ofMTJ 1161, non-magnetic spacing layer 1122 is shown formed on top of caplayer 1120, UL 1128 is shown formed on top of non-magnetic spacing layer1122, MTJ 1162 is shown formed on top of UL 1128, cap layer 1141 isshown formed on top of MTJ 1162, and TE 1143 is shown formed on top ofcap layer 1141.

In FIG. 24, the magnetic anisotropy of each of the free and fixed layersof MTJ 1161 is perpendicular and the magnetic anisotropy of each of thefree and fixed layers of MTJ 1162 is perpendicular. It should be notedthat in some embodiments, the NCC of each of the composite free layersof the MTJs 1161 and 1162 include different amounts of non-magneticalloys. In another embodiment, the NCC of each of the composite freelayers of the MTJs 1161 and 1162 is made of essentially similar alloysbut have different thickness.

FIG. 25 shows multi-state STTMRAM 1800, in accordance with anotherembodiment of the present invention. In the embodiment of FIG. 25,multi-state STTMRAM 1800 is shown to include BE 1104, UL 1106, MTJ 1502,cap layer 1120, non-magnetic spacing layer 1122, AFM layer 1154, MTJ1162, cap layer 1141 and TE 1143. UL 1106 is shown formed on BE 1104,MTJ 1502 is shown formed on top of UL 1106, cap layer 1120 is shownformed on top of MTJ 1502, non-magnetic spacing layer 1122 is shownformed on top of cap layer 1120, AFM layer 1154 is shown formed on topof non-magnetic spacing layer 1122, MTJ 1162 is shown formed on top ofUL 1128, cap layer 1141 is shown formed on top of MTJ 1162, and TE 1143is shown formed on top of cap layer 1141.

In FIG. 25, the magnetic anisotropy of each of the free and fixed layersof MTJ 1502 is in-plane and the magnetic anisotropy of each of the freeand fixed layers of MTJ 1162 is perpendicular.

While various combinations of MTJs are shown in FIGS. 10 through 25,such as in-plane, perpendicular, with/without AFM layer, with/withoutNCC, and the like, various other combinations and configurations of MTJsare contemplated.

In each of the embodiments of FIGS. 10 through 25, while two MTJs areshown, any number of MTJs may be employed. Moreover, the perpendicularvs. in-plane MTJs not only may alternate but they may also be everyconfigured to be of the same orientation for some number of MTJs thatare stacked on top of each other prior to a MTJ having an oppositeorientation being formed thereon. Any such combination is contemplated.

FIG. 26 shows a flow chart of the steps performed, during a write orprogram operation, to write/program one or more of the MTJs of thevarious embodiments of the present invention. In FIG. 26, process 1900outlines relevant steps of the write operation.

In one embodiment of the present invention, the steps of process 1900 ofFIG. 16 are performed by the program/erase circuit 900 of FIG. 8. Atstep 1902, data to be programmed is received. Next, a determination ismade at 1904 as to whether or not the most significant bit (MSB) of thereceived data is the value ‘0’ and if so, process 1900 proceeds to step1908, otherwise, process 1900 proceeds to step 1906. At step 1906, anegative high (H) current is applied to the MTJ or memory cell beingprogrammed. In one embodiment, the memory cell sought to be programmedis MTJ 912, in other embodiments, the MTJ sought to be programmed is anyone of the memory cells that include one or more of the MTJs of thevarious embodiments of the present invention.

Negative H current, as used herein, refers to sufficient negativecurrent allowing switching (or changing states) of an MTJ having no NCCand being programmed. Negative low current, as used herein, refers tosufficient negative current allowing switching (or changing states) ofan MTJ having NCC and being programmed. Positive H current, as usedherein, refers to sufficient positive current allowing switching (orchanging states) of an MTJ not having NCC and being programmed. Positivelow current, as used herein, refers to sufficient positive currentallowing switching (or changing states) of an MTJ including NCC andbeing programmed.

Referring back to process 1900, at step 1908, positive H current isapplied to the MTJ being programmed. Next, after step 1908, adetermination is made at 1910 as to whether or not the least significantbit (LSB) of the received data is zero and if not, process 1900 proceedsto step 1920, otherwise, process 1900 proceeds to step 1914. At step1920, a negative low current is applied to the MTJ being programmed atstep 1914, no current or zero current is applied to the MTJ beingprogrammed. After step 1914, process 1900 proceeds to the end of theprogramming step 1922. Similarly, after step 1920, process 1900 proceedsto the end of the programming step 1922.

After step 1906, a determination is made at 1912 as to whether or notthe LSB of the received data is zero and if not, process 1900 proceedsto step 1918, otherwise, process 1900 proceeds to step 1916. At step1918, zero or no current is applied to the MTJ being programmed at step1916, positive low current is applied to the MTJ being programmed. Afterstep 1916, process 1900 proceeds to the end of the programming step1922. Similarly, after step 1918, process 1900 proceeds to the end ofthe programming step 1922.

In alternative embodiments of the present invention, the MTJs (or memoryelements) disclosed in U.S. patent application Ser. No. 11/674,124entitled “Non-Uniform Switching Based Non-Volatile Magnetic BaseMemory”, filed on Feb. 12, 2007, may be employed in the embodiments ofFIGS. 8 and 9 herein.

It should be noted that the objects of the drawings or figures discussedand presented herein are not necessarily drawn to scale.

In some embodiment, those free or fixed layers of the STTMRAMs 1100,1153, 1155, 1160, 1164, 1166 and 1700 that have perpendicularorientation, as shown in the FIGS. 10, 11, 12, 13, 14, 15 and 24, havelargely a circular (or cylindrical) shape in-plane. This is furtherdescribed in US Patent Publication No. US 2008/019125 entitled,“Non-Volatile Magnetic Memory With Low Switching Current And HighThermal Stability”, the contents of which is incorporated herein byreference as though set forth in full. This is particularly usefulduring manufacturing of such STTMRAM, especially for smaller featuresizes such as below 90 nano meters (nm) because the in-plane STTMRAMtypically requires an elongated shape such as rectangular or ellipse,having an aspect ratio of two or three; such designs are difficult toform with high degree of uniformity for smaller feature sizes below 90nm and pose a greater design and cost challenge for the photo-masksrequired for printing such structures. The perpendicular STTMRAM, on theother hand, requires an aspect ratio closer to one and this does notrequire special designs for the photo-mask requiring high-aspect ratioshape control like the in-plane STTRAM.

In some embodiments, where the STTMRAMs 1170, 1180, 1192, 1200, 1300,1400, 1500, 1600 and 1800 have both longitudinal (or in-plane) andperpendicular MTJs, as shown in FIGS. 16, 17, 18, 19, 20, 21, 22, 23 and25, the preferred in-plane shape is rectangular or ellipsoid as shown inFIG. 27( b). It is likely that such designs may not be scalable wellbelow 65 nm feature size for the reasons mentioned above.

FIG. 27( a) shows top-down or in-plane view and side-view of shapes thatany of the STTMRAMs 1100, 1153, 1155, 1160, 1164, 1166 or 1700 can havewhen their free and fixed layers have perpendicular magneticorientation. In this case, the shape of the STTMRAM is substantiallycircular or cylindrical.

FIG. 27( b) shows top-down or in-plane view and side-view of shapes thatany of the STTMRAMs 1170, 1180, 1192, 1200, 1300, 1400, 1600 or 1700 canhave when their free and fixed layers have in-plane (or longitudinal)magnetic orientation. In this case, the shape of the STTMRAM issubstantially oval or rectangular.

Although the present invention has been described in terms of specificembodiments, it is anticipated that alterations and modificationsthereof will no doubt become apparent to those skilled in the art. It istherefore intended that the following claims be interpreted as coveringall such alterations and modification as fall within the true spirit andscope of the invention.

What is claimed is:

TABLE 1 MLC cell with two or more stacked MTJ with differentanisotrophy. I density 100 n = 2 Parallel Anti-parallel Anisotrophyratio 2 R(K Ω) large 1 2 Large Small R(K Ω) small 2 4 Fixed layers Freelayer 1 Free layer 2 State Total R Prog I (uA) → → → 1 3 200 → → ← 2 5−50 → ← ← 3 6 −200 → ← → 4 4 50

TABLE 2 MLC cell with two or more MTJs side by side with differentanisotrophy. I density 50 n = 2 Parallel Anti-parallel Anisotrophy ratio1.3 R(K Ω) large 3 6 Small Large R(K Ω) small 3.9 7.8 Fixed layer Freelayer Free layer State Total R Prog I (uA) → → → 1 1.70 −134.5 → → ← 22.36 50 → ← ← 3 3.39 134.5 → ← → 4 2.17 −50 From one state to another 1to 2 2 to 3 3 to 4 R differences 0.67 1.03 1.22 0.47 between differentstates

1. A multi-state spin-torque transfer magnetic random access memory(STTMRAM) formed on a film and comprising: a first magnetic tunnelingjunction (MTJ) having a first fixed layer, a first sub-magnetic tunneljunction (sub-MTJ) layer formed on top of the first fixed layer, and afirst free layer formed on top of the first sub-MTJ layer, the firstfixed layer and first free layer each having a first magneticanisotropy; non-magnetic spacing layer formed on top of the first MTJlayer; and a second MTJ formed on top of the non-magnetic spacing layerand having a second fixed layer, a second sub-MTJ layer and a secondfree layer, the second sub-MTJ layer formed on top of the second fixedlayer, the second free layer formed on top of the second sub-MTJ layer,the second fixed and second free layers each having a second magneticanisotropy, wherein at least one of the first or second magneticanisotropy is perpendicular to the plane of the film.
 2. The multi-stateSTTMRAM, as recited in claim 1, further including a first cap layerformed on top of the first free layer.
 3. The multi-state STTMRAM, asrecited in claim 2, further including a second cap layer formed on topof the second free layer.
 4. The multi-state STTMRAM, as recited inclaim 3, further including a top electrode (TL) formed on top of thesecond cap layer.
 5. The multi-state STTMRAM, as recited in claim 1,wherein the first and second magnetic anisotropy are perpendicular tothe plane film.
 6. The multi-state STTMRAM, as recited in claim 5,wherein the first sub-magnetic tunnel junction (sub-MTJ) layer includesa first spin polarization enhanced layer (SPEL), a first tunneling layerformed on top of the first SPEL and a second SPEL formed on top of thefirst tunneling layer.
 7. The multi-state STTMRAM, as recited in claim6, wherein the second free layer is a second composite free layer. 8.The multi-state STTMRAM, as recited in claim 7, wherein the compositefree layer comprises a first sub-free layer, a nano-current channel(NCC) layer formed on top of the first sub-free layer and a secondsub-free layer formed on top of the NCC layer.
 9. The multi-stateSTTMRAM, as recited in claim 10, wherein the second sub-magnetic tunneljunction (sub-MTJ) layer includes a third SPEL, a second tunneling layerformed on top of the third SPEL and a fourth SPEL formed on top of thesecond tunneling layer.
 10. The multi-state STTMRAM, as recited in claim1, further including a bottom electrode (BE) formed on top of the film.11. The multi-state STTMRAM, as recited in claim 10, further including afirst underlayer formed on top of the BE.
 12. The multi-state STTMRAM,as recited in claim 11, further including a first anti-ferromagnetic(AFM) formed on top of the first underlayer.
 13. The multi-stateSTTMRAM, as recited in claim 11, further including a second underlayerformed on top of the non-magnetic spacing layer.
 14. The multi-stateSTTMRAM, as recited in claim 13, further including a second AFM layerformed on top of the second underlayer.
 15. The multi-state STTMRAM, asrecited in claim 13, further including a second AFM layer formed on topof the second underlayer.
 16. The multi-state STTMRAM of claim 6,wherein the first free layer is a first composite free layer.
 17. Themulti-state STTMRAM of claim 16, wherein the first composite free layercomprises a first sub-free layer, a nano-current channel (NCC) layerformed on top of the first sub-free layer and a second sub-free layerformed on top of the NCC layer.
 18. The multi-state STTMRAM of claim 5,wherein the first sub-magnetic tunnel junction (sub-MTJ) layer comprisesa first spin polarization enhanced layer (SPEL), a first tunneling layerformed on top of the first SPEL, and a second SPEL formed on top of thefirst tunneling layer.
 19. The multi-state STTMRAM of claim 18, whereinthe second sub-MTJ layer comprises a third SPEL layer, a secondtunneling layer formed on top of the third SPEL, and a fourth SPELformed on top of the second tunneling layer.
 20. The multi-state STTMRAMof claim 19, wherein the second free layer formed on top of the secondsub-MTJ layer is a first composite free layer.
 21. The multi-stateSTTMRAM of claim 7, wherein the first sub-magnetic tunnel junction(sub-MTJ) layer comprises a first spin polarization enhanced layer(SPEL), a first tunneling layer formed on top of the first SPEL, and asecond SPEL formed on top of the first tunneling layer.
 22. Themulti-state STTMRAM of claim 21, wherein the second sub-MTJ layercomprises a third SPEL layer, a second tunneling layer formed on top ofthe third SPEL, and a fourth SPEL formed on top of the second tunnelinglayer.
 23. The multi-state STTMRAM of claim 22, wherein the second freelayer formed on top of the second sub-MTJ layer is a first compositefree layer.
 24. The multi-state STTMRAM of claim 12, wherein the firstsub-magnetic tunnel junction (sub-MTJ) layer comprises a first spinpolarization enhanced layer (SPEL), a first tunneling layer formed ontop of the first SPEL, and a second SPEL formed on top of the firsttunneling layer.
 25. The multi-state STTMRAM of claim 24, wherein thesecond sub-MTJ layer comprises a third SPEL layer, a second tunnelinglayer formed on top of the third SPEL, and a fourth SPEL formed on topof the second tunneling layer.
 26. The multi-state STTMRAM of claim 13,wherein the first sub-magnetic tunnel junction (sub-MTJ) layer comprisesa first spin polarization enhanced layer (SPEL), a first tunneling layerformed on top of the first SPEL, and a second SPEL formed on top of thefirst tunneling layer.
 27. The multi-state STTMRAM of claim 26, whereinthe second sub-MTJ layer comprises a third SPEL layer, a secondtunneling layer formed on top of the third SPEL, and a fourth SPELformed on top of the second tunneling layer.
 28. The multi-state STTMRAMof claim 27, wherein the first free layer formed on top of the firstsub-MTJ layer is a first composite free layer.
 29. The multi-stateSTTMRAM of claim 28, wherein the second free layer formed on top of thesecond sub-MTJ layer is a second composite free layer.
 30. Themulti-state STTMRAM of claim 29, wherein the first composite free layercomprises a first sub-free layer, a nano-current channel (NCC) layerformed on top of the first sub-free layer and a second sub-free layerformed on top of the NCC layer.
 31. The multi-state STTMRAM of claim 10,wherein the first sub-magnetic tunnel junction (sub-MTJ) layer comprisesa first spin polarization enhanced layer (SPEL), a first tunneling layerformed on top of the first SPEL, and a second SPEL formed on top of thefirst tunneling layer.
 32. The multi-state STTMRAM of claim 31, whereinthe second sub-MTJ layer comprises a third SPEL layer, a secondtunneling layer formed on top of the third SPEL, and a fourth SPELformed on top of the second tunneling layer.
 33. The multi-state STTMRAMof claim 32, wherein the first free layer formed on top of the firstsub-MTJ layer is a first composite free layer.
 34. The multi-stateSTTMRAM of claim 33, wherein the second free layer formed on top of thefirst sub-MTJ layer is a first composite free layer.
 35. The multi-stateSTTMRAM of claim 34, wherein the first composite free layer comprises afirst sub-free layer, a nano-current channel (NCC) layer formed on topof the first sub-free layer and a second sub-free layer formed on top ofthe NCC layer.
 36. The multi-state STTMRAM of claim 31, wherein thefirst magnetic anisotropy is perpendicular to the plane of the film, andthe second magnetic anisotropy is parallel to the plane of the film. 37.The multi-state STTMRAM of claim 22, wherein the first magneticanisotropy is perpendicular to the plane of the film, and the secondmagnetic anisotropy is parallel to the plane of the film.
 38. Themulti-state STTMRAM of claim 23, wherein the first magnetic anisotropyis perpendicular to the plane of the film, and the second magneticanisotropy is parallel to the plane of the film.
 39. The multi-stateSTTMRAM of claim 29, wherein the first magnetic anisotropy is parallelto the plane of the film, and the second magnetic anisotropy isperpendicular to the plane of the film.
 40. The multi-state STTMRAM ofclaim 30, wherein the first magnetic anisotropy is parallel to the planeof the film, and the second magnetic anisotropy is perpendicular to theplane of the film.
 41. The multi-state STTMRAM of claim 32, wherein thefirst magnetic anisotropy is perpendicular to the plane of the film, andthe second magnetic anisotropy is parallel to the plane of the film. 42.The multi-state STTMRAM of claim 33, wherein the first magneticanisotropy is perpendicular to the plane of the film, and the secondmagnetic anisotropy is parallel to the plane of the film.
 43. Themulti-state STTMRAM of claim 34, wherein the first magnetic anisotropyis perpendicular to the plane of the film, and the second magneticanisotropy is parallel to the plane of the film.
 44. The multi-stateSTTMRAM of claim 35, wherein the first magnetic anisotropy isperpendicular to the plane of the film, and the second magneticanisotropy is parallel to the plane of the film.
 45. The multi-stateSTTMRAM of claim 17, wherein the first magnetic anisotropy is parallelto the plane of the film, and the second magnetic anisotropy is parallelto the plane of the film.
 46. The multi-state STTMRAM of claim 1,further including more than two MTJs.
 47. The multi-state STTMRAM ofclaim 1, wherein the shape of the STTMRAM is circular.
 48. Themulti-state STTMRAM of claim 1, wherein the shape of the STTMRAM iscylindrical.
 49. The multi-state STTMRAM of claim 1, wherein the shapeof the STTMRAM is rectangular.
 50. The multi-state STTMRAM of claim 1,wherein the shape of the STTMRAM is oval.